The first lookup table also implements a multiplexer having an output and inputs coupled to the n selectable taps, and the shift register operable at a shift frequency at which data are shifted responsive to a first clock frequency, and the n taps are selectable at a select-frequency responsive to a second clock frequency that is m× the first clock frequency, wherein m is an integer and The linear feedback shift register of claim 1, wherein: A linear feedback shift register in a programmable gate array, comprising:Ī first lookup table configured as a shift register having n selectable taps and a shift-input, wherein n is an integer andĪ second lookup table configured as a parity generator having inputs coupled to the n selectable taps and an output coupled to the shift-input shift register.Ģ.
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